SRAM occupies more than 50% of die area in high-Performance SoCs. Device variations in advanced technology Nodes limit SRAM cell performance and yield. Maximum read Time defines performance yield limited yield for SRAMs. In this Work, we estimate the sensitivity of reading time of a 6T SRAM cell to Variations in different devices through Design of Experiments (Doe) method. We evaluate multiple read time models and Estimate variations in yield forgiving read time specification.
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