Friday, 24 October 2014

Analysis of Different Topology and Topology Implementation for Performance Enhancement of NOC Architecture

With Moore’s law supplying billions of transistors, the component density is scaling at a much faster rate than the wire density and the pin density leading to performance limitations. Also, most of the power is used to drive wires and clock cycle is spent on wire delays and not on gate delays. As a result, packet -switched on-chip networks are fast replacing buses and crossbars. Therefore, performance analysis of these interconnection networks which is used to transport data between different subsystems becomes necessary.For performance analysis of different parameter of NOC, we haven different types of simulator available with us like BookSim, Noxim, Nirgam etc. Performance analysis of different topologies can be done with the aid of these simulators as these are designed to let us change different properties like topology, the routing function, traffic pattern, injection rate. We have used the BookSim simulator for our analysis Different performance parameters like latency, throughput, injection rate, hop count can be obtained by changing the properties in this networks.

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